The Spin Semiconductor FV-1 is a complete reverb solution in a single IC. With integrated stereo ADC and DACs, the FV-1 can be treated like any other analog component in your products signal path.

The FV-1 can access a total of 16 programs, 8 are built in to the internal ROM and the designer may elect to connect a serial EEPROM with 8 additional programs. By using an external EEPROM, the designer can distinguish his product from others by creating a custom program set without the need for a microprocessor in the system.

With 3 potentiometer inputs, programs may have real time variable parameters such as decay time in a reverb, rate and depth in a chorus or frequency in a filter. These inputs are available as coefficients to your program and may be used independently of each other.

The rich instruction set allows users to program effects of all kinds. With instructions like LOG and EXP, users can easily program audio expansion and compression routines. Integrated digital LFOs and ramp generators allow for programming chorus, flange and pitch shift.

Code:

```
RDA : DRAM[ADDR] * C + ACC
RMPA : DRAM[PNTR[N]] * C + ACC
WRA : ACC->DRAM[ADDR] , ACC * C
WRAP : ACC->DRAM[ADDR] ,(ACC * C) + LR
RDAX : C * REG[ADDR] + ACC
RDFX : (ACC - REG[ADDR]) * C + REG[ADDR]
WRAX : ACC->REG[ADDR] , C * ACC
WRHX : ACC->REG[ADDR] , (ACC * C)+PACC
WRLX : ACC->REG[ADDR] , (PACC - ACC) * C + PACC
MAXX : MAX( |REG[ADDR] * C| , |ACC|)
MULX : ACC * REG[ADDR]
LOG : C * LOG(|ACC|) + D
EXP : C * EXP(ACC) + D
SOF : C + ACC + D
AND : ACC & MASK
OR : ACC | MASK
XOR : ACC ^ MASK
SKP : SKIP [CONDITION] LINES
WLDS : LOAD FREQ & AMPLITUDE INTO SIN LFO
WLDR : LOAD FREQ & AMPLITUDE INTO RAMP LFO
JAM : RESET A SELECTED LFO
CHO : CHORUS COMMAND
NOP : NO OPERATION
NOT : LOGICAL NOT
CLR : CLEAR ACC
ABSA : ACC = ABS(ACC)
LDAX : ACC = REGISTER
```

Code:

```
SIN0_RATE : 0x00 (0 : Sine LFO 0 rate
SIN0_RANGE : 0x01 (1 : Sine LFO 0 range
SIN1_RATE : 0x02 (2 : Sine LFO 1 rate
SIN1_RANGE : 0x03 (3 : Sine LFO 1 range
RMP0_RATE : 0x04 (4 : Ramp LFO 0 rate
RMP0_RANGE : 0x05 (5 : Ramp LFO 0 range
RMP1_RATE : 0x06 (6 : Ramp LFO 1 rate
RMP1_RANGE : 0x07 (7 : Ramp LFO 1 range
POT0 : 0x10 (16 : Pot 0 input register
POT1 : 0x11 (17 : Pot 1 input register
POT2 : 0x12 (18 : Pot 2 input register
ADCL : 0x14 (20 : ADC input register left channel
ADCR : 0x15 (21 : ADC input register right channel
DACL : 0x16 (22 : DAC output register left channel
DACR : 0x17 (23 : DAC output register right channel
ADDR_PTR : 0x18 (24 : Used with 'RMPA' instruction for indirect read
REG0 : 0x20 (32 : Register 00
REG1 : 0x21 (33 : Register 01
REG2 : 0x22 (34 : Register 02
REG3 : 0x23 (35 : Register 03
REG4 : 0x24 (36 : Register 04
REG5 : 0x25 (37 : Register 05
REG6 : 0x26 (38 : Register 06
REG7 : 0x27 (39 : Register 07
REG8 : 0x28 (40 : Register 08
REG9 : 0x29 (41 : Register 09
REG10 : 0x2A (42 : Register 10
REG11 : 0x2B (43 : Register 11
REG12 : 0x2C (44 : Register 12
REG13 : 0x2D (45 : Register 13
REG14 : 0x2E (46 : Register 14
REG15 : 0x2F (47 : Register 15
REG16 : 0x30 (48 : Register 16
REG17 : 0x31 (49 : Register 17
REG18 : 0x32 (50 : Register 18
REG19 : 0x33 (51 : Register 19
REG20 : 0x34 (52 : Register 20
REG21 : 0x35 (53 : Register 21
REG22 : 0x36 (54 : Register 22
REG23 : 0x37 (55 : Register 23
REG24 : 0x38 (56 : Register 24
REG25 : 0x39 (57 : Register 25
REG26 : 0x3A (58 : Register 26
REG27 : 0x3B (59 : Register 27
REG28 : 0x3C (60 : Register 28
REG29 : 0x3D (61 : Register 29
REG30 : 0x3E (62 : Register 30
REG31 : 0x3F (63 : Register 31
SIN0 : 0x00 (0 : USED with 'CHO' : SINE LFO 0
SIN1 : 0x01 (1 : USED with 'CHO' : SINE LFO 1
RMP0 : 0x02 (2 : USED with 'CHO' : RAMP LFO 0
RMP1 : 0x03 (3 : USED with 'CHO' : RAMP LFO 1
RDA : 0x00 (0 : USED with 'CHO' : ACC += ( DRAM * COEFF)
SOF : 0x02 (2 : USED with 'CHO' : ACC = ( ACC * LFO COEFF) + Constant
RDAL : 0x03 (3 : USED with 'CHO' : Reads value of selected LFO into the ACC
SIN : 0x00 (0 : USED with 'CHO' : SIN/COS from SINE LFO
COS : 0x01 (1 : USED with 'CHO' : SIN/COS from SINE LFO
REG : 0x02 (2 : USED with 'CHO' : Save LFO temp reg in LFO block
COMPC : 0x04 (4 : USED with 'CHO' : 2's comp : Generate 1-x for interpolate
COMPA : 0x08 (8 : USED with 'CHO' : 1's comp address offset (Generate SIN or COS)
RPTR2 : 0x10 (16 : USED with 'CHO' : Add 1/2 to ramp to generate 2nd ramp for pitch shift
NA : 0x20 (32 : USED with 'CHO' : Do NOT add LFO to address and select cross-face coefficient
RUN : 0x80000000 USED with 'SKP' : Skip if NOT FIRST time through program
ZRC : 0x40000000 USED with 'SKP' : Skip On Zero Crossing
ZRO : 0x20000000 USED with 'SKP' : Skip if ACC = 0
GEZ : 0x10000000 USED with 'SKP' : Skip if ACC is' >= 0'
NEG : 0x8000000 USED with 'SKP' : Skip if ACC is Negative
COS0 : 0x08 (8 : USED with 'CHO' : COSINE LFO 0
COS1 : 0x09 (9 : USED with 'CHO' : COSINE LFO 1
```

**FV-1 Instructions and Syntax**

EQU

EQU

Equate a value to a label reference

**Usage:**

Code:

```
equ krt 0.86 ;equate the label krt to the value of 0.86
equ sgn -1 ;equate the label sgn to the value of -1
equ a reg0 ;equate the label a to represent register 0
```

**Notes:**

- declare label equates prior to label use.

**MEM**

Define the length of delay memory elements and associate an address label.

**Usage:**

Code:

`mem del1 1000 ;assign 1000 delay memory locations to the label del1`

**Notes:**

- when writing to a delay, do so to the address label
- when reading the end of the delay, do so to the address label terminated with a #, as in del1#
- when reading the midpoint of a delay, do so to the address label terminated with a $, as in del1$

**RDA**

Read delay memory times coefficient and add to accumulator.

**Usage:**

Code:

`rda memaddress,coefficient`

**Notes:**

- coefficient width is 11 bits, ranging -2.0 to +1.998
- read data from delay memory is simultaneously loaded into the LR register
- Previous ACC value is simultaneously loaded into PACC

**RMPA**

Read delay memory from addr_ptr location, multiply by coefficient and add to accumulator

**Usage:**

Code:

`rmpa coefficient`

**Notes:**

- addr_ptr is a special register reserved for delay memory addressing
- coefficient width is 11 bits, ranging -2.0 to +1.998
- read data from delay memory is simultaneously loaded into the LR register
- Previous ACC value is simultaneously loaded into PACC

**WRA**

Write ACC to delay memory location and multiply ACC by coefficient

**Usage:**

Code:

`wra memaddrs,coefficient`

**Notes:**

- coefficient width is 11 bits, ranging -2.0 to +1.998
- Previous ACC value is simultaneously loaded into PACC

**WRAP**

Write delay memory, multiply written value by the coefficient, add to LR register and load ACC with result.

**Usage:**

Code:

`wrap memaddrs,coefficient`

**Notes:**

- used specifically in producing inline all pass filters for reverb.
- coefficient width is 11 bits, ranging -2.0 to +1.998
- Previous ACC value is simultaneously loaded into PACC

rda ap1#,kap

wrap ap1,-kap

where previous statements defined ap1 and kap:

mem ap1 205 ;ap1 is 205 memory locations long

equ kap 0.55 ;all pass coefficient is 0.55

**RDAX**

Read register value, multiply by coefficient and add to ACC.

**Usage:**

Code:

```
rdax reg0,0.2
rdax hifil,kfil ;hifil previously equated to register (such as reg12), kfil previously equated to numerical value.
```

**Notes:**

coefficient width is 16 bits, ranging -2.0 to +1.9999389

Previous ACC value is simultaneously loaded into PACC

back to FV-1 Instructions and Syntax top

**RDFX**

Subtract register contents from ACC, multiply by coefficient, add register contents and load to ACC.

**Usage:**

Code:

`rdfx reg0,0.23`

**Notes:**

- Used specifically for the construction of filters.
- coefficient width is 16 bits, ranging -2.0 to +1.9999389
- Previous ACC value is simultaneously loaded into PACC

RDFX reg,1

**WRAX**

Write ACC to register, multiply ACC by coefficient

**Usage:**

Code:

`wrax reg1,0`

**Notes:**

- Coefficient width is 16 bits, ranging -2.0 to +1.9999389
- Previous ACC value is simultaneously loaded into PACC

**WRHX**

Write ACC to register, multiply ACC by coefficient, add PACC and load result to ACC

**Usage:**

Code:

`wrhx reg2,-0.5`

**Notes:**

- Used in creating single pole, shelving high pass filters.
- The coefficient should be negative and will create a shelf gain based on the coefficient value.
- Coefficient width is 16 bits, ranging -2.0 to +1.9999389
- Previous ACC value is simultaneously loaded into PACC

rdfx reg0,khp ;khp previously defined with an EQU statement

wrhx reg0,ksh ;ksh previously defined with an EQU statement

The input signal will be in ACC, and during the execution of the first statement, that input signal will be transferred to PACC. During the second instruction, the written value is multiplied by a coefficient (which would be negative for a shelf), and added to PACC (the original input signal). The coefficient in the first instruction sets the corner frequency of the filter, and the coefficient in the second instruction determines the shelf depth. A coefficient of -1.0 represents an infinite shelf, a coefficient of -0.5 sets a shelf at -6dB.

**WRLX**

Write ACC to the register, subtract ACC from PACC, multiply result by the coefficient, then add PACC and load result to ACC.

**Usage:**

Code:

`wrlx reg6,kshlf ;kshlf previously equated to a numerical value.`

**Notes:**

- Used in creating single pole, shelving low pass filters.
- The coefficient should be negative and will create a shelf gain based on the coefficient value.
- Coefficient width is 16 bits, ranging -2.0 to +1.9999389
- Previous ACC value is simultaneously loaded into PACC

rdfx reg0,klp ;klp previously defined with an EQU statement

wrlx reg0,ksh ;ksh previously defined with an EQU statement

The input signal will be in ACC, and during the execution of the first statement, that input signal will be transferred to PACC. During the second instruction, the written value is subtracted from PACC (the filter's input signal), multiplied by the shelving coefficient and added to PACC (the original input signal). The coefficient in the first instruction sets the corner frequency of the filter, and the coefficient in the second instruction determines the shelf depth. A coefficient of -1.0 represents an infinite shelf, a coefficient of -0.5 sets a shelf at -6dB.

**MAXX**

Load the maximum of the absolute value of the register times the coefficient or the absolute value of ACC to ACC.

**Usage:**

Code:

`maxx reg2,0.5`

**Notes:**

- Coefficient width is 16 bits, ranging -2.0 to +1.9999389
- Previous ACC value is simultaneously loaded into PACC

maxx reg0,0.99

wrax reg0,0

The first instruction compares the value in reg0 with the accumulator, but does so with a somewhat decreased reg0 value; this is so that if the ACC signal is smaller, the second instruction will write this decreased value back to reg0. Otherwise, the ACC value will be forced into reg0. The coefficient in the second instruction leaves ACC cleared, but if the coefficient is 1, then the peak detected signal will be passed on to further processing. The coefficient in the first instruction will determine the time constant of the filter.

**ABSA**

Changes the ACC contents to absolute value of ACC

**Notes:**Previous ACC value is simultaneously loaded into PACC

**MULX**

Load the accumulator with the product of ACC and a register.

**Usage:**

Code:

`mulx reg0`

**Notes:**

The upper 15 bits of the register are used as a coefficient, allowing a multiplier range of -1.0 to +0.999389

Previous ACC value is simultaneously loaded into PACC

**LOG**

Take the LOG base 2 of the absolute value of the accumulator, divide result by 16, multiply the result by the coefficient, add a constant and load to ACC.

**Usage:**

Code:

`log 1.5,-0.3`

**Notes:**

- Coefficient width is 16 bits, ranging -2.0 to +1.9999389
- constant width is 11 bits, -1.0 to +0.999
- Previous ACC value is simultaneously loaded into PACC
- This function, along with EXP provides the ability to perform divides and square roots.

**EXP**

Raise 2 to the power of the accumulator*16, multiply by a coefficient and add to a constant, loading the result to ACC.

**Usage:**

Code:

`exp 0.8,0`

**Notes:**

- Coefficient width is 16 bits, ranging -2.0 to +1.9999389
- constant width is 11 bits, -1.0 to +0.999
- Previous ACC value is simultaneously loaded into PACC
- This function, along with LOG provides the ability to perform divides and square roots.
- The EXP function is designed tocompliment the LOG function.

**SOF**

Multiply ACC by the coefficient value and add a constant (Scale and OFfset)

**Usage:**

Code:

`SOF 1.5,-0.3 ;multiply the accumulator by 1.5 and subtract 0.3`

**Notes:**

- Coefficient width is 16 bits, ranging -2.0 to +1.9999389
- constant width is 11 bits, -1.0 to +0.999
- Previous ACC value is simultaneously loaded into PACC

**AND**

And ACC with immediate mask

**Usage:**

Code:

```
and %011111000000000000000000 ;and with binary 011111000000000000000000
and $000001 ;and with hex 000001
```

**Notes:**

Previous ACC value is simultaneously loaded into PACC

**OR**

Or ACC with immediate mask

**Usage:**

Code:

```
or %011111000000000000000000 ;or with binary 011111000000000000000000
or $000001 ;or with hex 000001
```

**XOR**

Xor ACC with immediate mask

**Usage:**

Code:

```
xor %011111000000000000000000 ;or with binary 011111000000000000000000
xor $000001 ;or with hex 000001
```

**Notes:**

Previous ACC value is simultaneously loaded into PACC

**SKP**

Skip N instructions based on condition

Usage:

Code:

```
skp zro,2 ;skip ahead 2 instructions if accumulator is zero.
skp gez,doit ;skip to label doit if accumulator is zero or positive
```

**Notes:**

Conditions are:

- run ;set after first program execution
- zrc ;if the sign of ACC and PACC are different
- zro ;if ACC is zero
- gez ;if ACC is greater than or equal to zero
- neg ;if ACC is negative

**WLDS**

Load SIN/COS generator with initial conditions

**Usage:**

Code:

`wlds sin0,freq,amp ;load the SIN/COS0 generator with freq and amp variables`

**Notes:**

- There are two SIN/COS generators in the FV-1, SIN0 and SIN1
- The frequency variable is a 9 bit value
- The amplitude variable is a 15 bit value
- This command is usually used to initialize a SIN/COS generator at the beginning of the program, preceded by a Skp run,1 command.

**WLDR**

Load RAMP generator with initial conditions

**Usage:**

Code:

`wldr rmp0,freq,amp ;load the RAMP0 generator with freq and amp variables`

**Notes:**

- There are two RAMP generators in the FV-1, RMP0 and RMP1
- The frequency variable is a 16 bit value
- The frequency variable is a 2 bit value 00 (0)=512, 01 (1)=1024, 10 (2)=2048 and 11 (3)=4096
- This command is usually used to initialize a RAMP generator at the beginning of the program, preceded by a Skp run,1 command.

**JAM**

When executed, will force a selected RAMP generator to it's starting condition

**Usage:**

Code:

`jam 0`

**Notes:**

- This can be used in pitch transposition to intelligently reset the read pointer when the input
- and output of the transpose function are highly correlated.

**CHO**

General operation for reading delay memory from an LFO output as both a memory pointer and an interpolation coefficient.

**Usage:**

Code:

```
cho rda,sin0, SIN | REG ,del1+100 ;read del1+100+(sine of SIN/COS0 value) also, register LFO values.
cho rdal,sin1 ;load accumulator with SIN/COS1 LFO output (Sine only)
cho sof,rmp1,na ;multiply ACC value by ramp1 crossfade value
```

The CHO RDA operation is intended to read memory from a location specified by the user, plus an address value from the selected LFO. The addressed value is multiplied by a fractional coefficient to form half of a signal interpolation between two adjacent points. The values from the LFO can be modified by a 6 bit number, inserted into the command line, that direxcts the process in several ways. The bits can be manually assembled into a number that is entered in decimal, HEX($-) or binary(%-). The 6 bits are as follows:

- Bit0: SIN (000000) or COS (000001) selects either the SIN or COS output of a SIN/COS generator
- Bit1: REG (000010) function. Using this will register the current LFO outputs for subsequent operations; to be used only on the first access to an LFO (LFO is continuously updated in the background)
- Bit2: COMPC(000100) sends 1-fraction to the multiplier for the first half of an interpolation.
- Bit3: COMPA(001000) compliments the address output, effectively inverting the SIN or COS function.
- Bit4: RPTR2(010000) Adds 0.5 of full scale to a RAMP, to obtain a second pointer in pitch transpose operations
- Bit5: NA(100000) Selects the crossfade function of a ramp generator for crossfading in a pitch transposer.
- The above bits can be used in OR fashion, such as: CHO RDA,S0,COS|REG|COMPC,del1+20

**NOP**

No operation

**Usage:**

Code:

`nop`

**NOT**

Change sign of ACC value

**Usage:**

Code:

`not`

**Notes:**

Previous ACC value is simultaneously loaded into PACC

**CLR**

Clear ACC

**Usage:**

Code:

`clr`

**Notes:**

Previous ACC value is simultaneously loaded into PACC

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