PT2399 Analysis -  CMOS Echo / Delay Processor

PT2399 Analysis - CMOS Echo / Delay Processor

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PT2399 Analysis -  CMOS Echo - Delay Processor.webp


The PT2399 is a CMOS echo/delay processor developed by Princeton Technology Corp. This digital chip includes an ADC (Analog to Digital converter), 44Kb of RAM to store the samples and a DAC (Digital to Analog converter). Although this chip was created as a simple solution to add delay/reverb/echo to karaokes and set-up entertainment systems, it became very popular in the guitar pedal community due to its ability to emulate BBD-based delay circuits, good price, through-hole package, 5V power supply and tolerance to modifications.

This integrated circuit has also demonstrated that with a careful design and good tuning, could be a fantastic sounding solution. Many well-known effects like Belton/Accu-Tronics reverb module, Danelectro FAB-Echo, and the Rebote Delay use this chip as the core of the circuit.

With a minimum delay of 30ms and a maximum of 340ms (that could be extended up to 1 second at the expense of sound quality) makes it perfect for delay, echo and reverb effects.

The official Princeton Technology PT2399 datasheet is vague and many of the internal functions of the IC are not explained either, giving the foundations for mods and think-out-of-the-box solutions. In this article, we are trying to give more insights and information about how this chip works.

PT2399 Internal Circuit:
The main problem with the PT2399 is to understand the internal circuit, the Princetown datasheet is not very helpful:

PT2399 Internal Circuit - 1.webp

This block diagram could be redrawn in a more logical and simpler way:

PT2399 Internal Circuit - 2.webp


This chip effectively includes 6 internal op-amps ( that the designer can use) and a power supply subsystem. In the next sections, the functionality of each part will be described.

The PT2399 is powered using 5V. In order to preserve the signal quality and reduce noise, it is convenient to use a dedicated supply or regulator. The part consumes a maximum current of 30mA (it decreases when the delay time is increased).

Controlling the Delay Time with pin6:
There are several ways to set the delay time using the pin6:

Using a potentiometer: This is the easiest way; following the datasheet suggestion use an external potentiometer of 10K ~ 50K (depending on the max delay time desired). A minimum resistor (R) of 2K is always needed (it will limit the minimum delay time), otherwise, the PT2399 will latch-up during the power-on sequence and the internal oscillator won't start.

Once the oscillator has started, there is no need for 2K a minimum resistor (R), this is why many designs include the anti-latch-up circuit, so the system starts with a high impedance on pin 6 and then it is removed after power on so the PT2399 can accomplish shorter delay times. There is no substantial benefit of grounding the pin 6, using an R smaller than 100ohms will just cause an increase in the current demand without shorting the delay time.

Controlling the Delay Time with pin6 - 1.webp


Use a transistor to limit the amount of current out of pin6. A PNP or NPN transistor could be used to limit the pin current. This method could be combined together with the anti-latch-up mod to ensure that the system will work under any condition.

Controlling the Delay Time with pin6 - 2.webp


The basic circuit (a) will limit the current flowing out of pin 6: the resistor R1 is needed so the range of the potentiometer can be limited in order to provide voltages from 0 to 0.65V to the base of the transistor (otherwise the potentiometer will work for a small portion of its whole span). R2 can be any small resistor 100 to 200Ω.

The second (b) circuit uses a resistor in parallel, in this way the maximum resistance of pin6 can be controlled and we can have a better control over the maximum delay time to be used. i.e using an R3 of 20K will give us a maximum of 270ms (following the datasheet table).

The last (c) schematic adds to the mix the anti-latch-up circuit, so we ensure that the circuit will always start under any condition (in case that during the power-on of the pedal (first 400ms) the Potentiometer is at its maximum position, setting the Q1 to ON and showing to pin 6 a low impedance.

PT2399 Input Stage:
The Input Stage consists of 3 op-amps. Two of them (2 and 3) are always used as part of the Sigma-Delta ADC circuit, so the designer cannot use them freely. The first op-amp is available to be used under any configuration, but the most common option is to use it as a filter/adder in a Multi-Feedback topology.

PT2399 Input Stage.webp


The Low-Pass Filter 1 aka Multi-Feedback Op-Amp Stage:
The first op-amp will filter the input stage removing the excess of high harmonics using a Multi-Feedback topology (MFB aka Infinite-Gain Multiple-Feedback).

The Low-Pass Filter 1 aka Multi-Feedback Op-Amp Stage.webp


The Multi-Feedback op-amp uses 2 poles (MFB-2) that give -12dB/octave of attenuation to the high-frequencies. The final filter (R5 and C3) adds an extra pole, making the total filter -18dB/octave. The MFB topology gives high gain / high Q with the inconvenient of more complex design calculations.

The MFB performs as good as a Sallen & Key filter (S&K uses 1 component less for unity gain filters though) but the MFB topology is chosen in this case it allows the op-amp to work as a summing amplifier, accepting a feedback path of the ECHO circuit.

There are several ways to calculate the values for the filter. Following the simple Elliot Sound Products method, it can be done like this:
fc = 1 / (2 x π x R x C) - Select R and C to have the desired cut frequency.

Then:
R1 = R2 = 2 x R
R3 = R
C1 = C / Q
C2 = (C x Q) / 2
R = 10K
C = 10nF

Where Q is 1/√2 = 0.707 for an ideal Butterworth filter.
Note: You can also use the Multiple Feedback Low-pass Filter Design Tool from Okawa-Denshi to calculate the values without doing all the mathematics.

The Delay circuit uses R1=15K, R2=10K, R3=15K, C1=3.9nF, and C2=0.56nF. Generating a fc=8.8kHz ( with a Q=0.9 )
The Echo circuit uses R1=15K, R2=10K, R3=10K, C1=5.6nF, and C2=0.56nF. Generating a fc=8.9kHz ( with a Q=1.1 )

The PT2399 shows a good performance with the input MFB filter tuned around 8.5kHz, with a wide frequency range and a reasonable low noise. The Delay circuit shows a combination of 10K and 15K resistors, there is no reason for doing that, you can stick to the same value (10K) and design the filter using just one resistor value.

The Delta-Sigma ADC Modulator:
In a Delta-Sigma (ΔΣ) modulator, the input audio signal is converted to a one-bit stream of logic levels which depend on the current direction (going high or going low) of the signal being converted. The clock rate is very high compared to the delayed audio signal's frequency in order to be able to use one-bit sampling.

The op-amps labelled as 2 and 3 in the image above are used in the processing of the one-bit data stream:
The output of the MFB op-amp is applied to the inverting input of the comparator, the non-inverting input of which is connected to the output of the modulator being fed by DO0.

DO0 (Data Out 0) is the output of a one-bit data latch into which the one bit converted audio data is stored until the next clock pulse.
The output of this latch feeds the 44K bit memory. The voltage on the comparator's inverting input will be compared to the output of the modulator (after low pass filtering) and will either go high or low depending on the difference detected. The output of the comparator is serially streamed into and through the PT2399's 44K bit memory.

The C3 capacitor is explained in the next section of this article.

PT2399 Output Stage:
The output stage consists of 2 op-amps. The first one has limited functionality and it is used as a low pass filter after the Demodulator (Anti-Aliasing Filter). The second op-amp is freely available and is again usually configured in a Multi-Feedback op-amp filter.
PT2399 Output Stage.webp


The output stage uses 1 op-amp as the Demodulator low-pass filter. This Reconstruction Filter will smooth the analog signal created by the Demodulator.

R6 is an internal resistor that is labelled as 4.7KΩ in the datasheet

The C6 (and C3) Capacitor forms a low pass filter in order to reduce the unwanted hi-frequencies, the datasheet suggests 100nF for delay and 82nF for the echo. There is no much info about the functionality of this caps. Lowering the values of C3 and C6 will allow more high harmonics to go through the chip and therefore a "more natural sound", of course, the drawback would be more digital noise into the signal. If you are using the PT2399 to do short delay/echo you can go as low as 22nF for C3 and C6, for longer delays (300ms) do not go lower than 47nF (100nF seems to be a good value for long delays).

Using 100nF on C3/C6, makes the delayed signal harmonics above 1kHz to be attenuated (see Frequency Response section), it is not catastrophic as the natural sound of a delayed/echoed signal has intrinsically less high content (real echoes usually have a rapidly diminishing HF content, as these harmonics are absorbed easily by the walls and air). A good middle ground value to allow more harmonics and less HF noise into the circuit would be 68nF.

The second op-amp is again in the MultiFeedBack topology (MFB), it will clean and smooth the signal even more.

R10 and C9 form a last low pass filter with a cut frequency of 5.8kHz (using a 2.7KΩ resistor and a10nF cap) or 2.8kHz (using a 5.6KΩ resistor and a 10nF cap). The drawback of this last filter is that it will raise the output impedance of the circuit, this can be solved by using a more sensible RC combination, with a smaller R and a higher C (like 10Ω and 4.7u that give fc=3.3kHz).

C10 is the output cap that removes any DC level from the output, any big value (4.7 / 10uF or similar) will work.

Frequency Response:
Using the basic DELAY schematic from the datasheet, the frequency response looks like this
Frequency Response.webp

The response is flat until the 1kHz area, after that the treble rolls down due to the Modulator and Demodulator caps (C3 and C6) and the two MFB filters. The lack of treble after 5kHz is not bad as the natural sound of delayed signal is less bright due to the walls and air absorption ( and also the guitar does not have many harmonics over that frequencies).

Reducing Noise in PT2399 designs:
In order to keep the noise figures measured in the PT2399 under control, some guidelines could be followed to ensure the best functionality out if this part:

Power Supply Design: Use a dedicated regulator for the PT2399; using a linear LM7805, LM2940 (or more complex LM317 or Zenner Follower) is a good idea.

Use a decoupling cap from Vcc (pin1) to the analog ground as close to the chip as possible.

Keep all the other caps (Modulator, Demodulator, MFB filters) as close to the IC as possible.

Pay attention to the analog and digital grounds: do not solder all the grounds together in an indiscriminate way. The correct way to do it, is to separate the analog and digital grounds (ideally each subsystem running on a start-ground configuration) and finally, connect the analog and digital grounds at one point, the best union point is a thick short trace between pins 3 and 4.

Capacitors: For longer delay times, the bandwidth of the system has to be limited, using big caps around 100nF on C3 (between pins 9 and 10) and C6 (between pins 11 and 12) will attenuate the HF the noise. Do not bother limiting the bandwidth of the MBF filters as they seem to not affect the HF noise response.

The Delay Circuit:
PT2399 Digital Delay Unit.webp


Super-Simple Delay Circuit:
Super-Simple PT2399 Delay Circuit-1.webp
 
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